Compute Express Link™: The Breakthrough CPU-to-Device Interconnect
Compute Express Link™ (CXL™): Link-level Integrity and Data Encryption (CXL IDE)
Airing Date: September 30, 2021
Security is a key cornerstone for any technology to be successful and CXL is making great strides in security by working collaboratively with other industry-standard bodies such as PCI-SIG and DMTF to ensure a seamless user experience with the best security mechanisms. CXL 2.0 enhances the security mechanism from CXL 1.1 and 1.0 by adding link-level Integrity and Data Encryption (CXL IDE) to provide confidentiality, integrity and replay protection for data transiting the CXL link.
This webinar will explore CXL IDE usage models and how security is managed across CXL.io, CXL.mem, CXL.cache and CXL Switches. The webinar will also explore a Device’s responsibility to maintain security.
Compute Express Link™ 2.0 Specification: Memory Pooling
Airing Date: March 23, 2021
Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. In November 2020, the CXL Consortium announced the CXL 2.0 specification which introduces support for switching, memory pooling, and support for persistent memory – all while preserving industry investments by supporting full backward compatibility.
In this webinar, Mahesh Wagh (Intel) and Rick Sodke (Microchip), will explore how CXL 2.0 supports memory pooling for multiple logical devices (MLD) as well as a single logical device with the help of a CXL switch. This presentation will also introduce the standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric
Memory Challenges and CXL Solutions
Airing Date: August 6, 2020
Compute Express Link™ (CXL™) is an industry supported cache-coherent interconnect for processors, memory expansion and accelerators. CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CXL.io, based on PCIe®), caching (CXL.cache) and memory (CXL.memory) semantics. CXL.mem allows a host processor to access memory attached to a CXL device. CXL.mem transactions are simple memory load and store transactions that run downstream from the host processor which takes care of all the associated coherency flows.
This webinar will explore how the CXL.mem protocol can deliver power-efficient performance with emerging applications such as AI, HPC, DL and comms with a coherent interface and low latency. This webinar will also explore type-3 devices and use cases for memory bandwidth expansion, memory capacity expansion and storage class memory.
Airing Date: June 15, 2021
Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification introduces support for switching, memory pooling, and persistent memory – all while preserving industry investments by supporting full backward compatibility.
An increasing number of applications — ranging from databases to AI workloads — are being enhanced to take advantage of persistent memory. This webinar will explore how the CXL specification has evolved to support persistent memory devices in a way that preserves the established software model. This webinar will cover enhancements to the CXL protocol, error handling, and standardized configuration interface, enabling innovative designs that are based on a variety of non-volatile media and form factors.
Introducing the Compute Express Link™ 2.0 Specification
Airing Date: December 10, 2020
The CXL™ Consortium is proud to announce the second-generation Compute Express Link™ (CXL™). CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices.
This webinar will explore the new features in the CXL 2.0 specification including support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory – all while preserving industry investments by supporting full backward compatibility with CXL 1.1 and 1.0.
Exploring Coherent Memory and Innovative Use Cases
Airing Date: March 12, 2020
Siamak Tavallaei, CXL Consortium Technical Task Force Co-Chair and Principal Architect, Microsoft Azure, Rob Blankenship, Processor Architect and Principal Engineer, Intel, and Kurt Lender, CXL Consortium Marketing Working Group Co-Chair and Senior Ecosystem Enabling Manager, Data Center Group, Intel, take listeners into a deep dive about CXL technology maintains memory coherency between the CPU memory space and memory on attached devices.
The webinar also details several representative CXL use cases – Caching Devices/Accelerators, Accelerators with Memory, and Memory Buffers.
Introduction to Compute Express Link™ (CXL)
Airing Date: December 12, 2019
A highly informative webinar about the CXL Consortium™ and its groundbreaking technology. Join Glenn Ward, CXL Consortium’s MWG Co-Chair and Chief of Staff, Cloud Server Infrastructure for Microsoft; Debendra Das Sharma, Intel Fellow at Intel Corporation; and Kurtis Bowman, CXL Consortium Board Member and Director, Server Architecture and Technologies at Dell EMC during this thought-provoking webinar about the organization and its innovative technology.
Topics covered include the industry landscape, features and benefits, use cases and more!