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Compute Express Link™: The Breakthrough CPU-to-Device Interconnect
Videos
CXL Technology Demonstrations:
Astera Labs Aries CXL™ Smart Retimers: Enabling Robust CXL Connectivity for Intel Sapphire Rapids CPU-base Systems with Synopsys DesignWare CXL Controller IP - Astera Labs
Cadence IP for CXL Interop Demonstration - Cadence
Proof of Concept: Memory Disaggregation Local, Expanded, and Remote Memory - Elastics.cloud
GigaIO: The Future of Composability with CXL - GigaIO
CXL Fabric Adaptor Bridge Demo - IntelliProp
CXL Type 3 Memory Device Demo - Meta
CXL™ IP/FPGA Platforms & Interoperability - Mobiveil
MXC + Retimer Video - Montage Technology
Demonstration of a CXL Interconnect on a FPGA-based Design - Rambus
Functional Integration of SAP HANA In-Memory-Database on Samsung's CXL Memory Expander - Samsung
Synopsys DesignWare CXL IP Showing Successful Data Transfer Using a Teledyne LeCroy CXL Analyzer - Synopsys
CXL Compliance Demonstration - Teledyne LeCroy
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