Compute Express Link™: The Breakthrough CPU-to-Device Interconnect
November 14-17, 2022
Kay Bailey Hutchison Convention Center, Dallas, TX
CXL Consortium will be hosting a booth (#2838) at the annual SC'22 event to showcase CXL technology demonstrations. Additionally, CXL representatives will be sharing information about the new features and usage models enabled in the CXL 3.0 specification and discussing the CXL device ecosystem at the Exhibitor Forum and Birds of a Feather sessions.
CXL member companies will be showcasing the following CXL technology demonstrations:
AMD – AMD SEV Enabled Confidential Containers on CXL Encrypted Memory
The AMD demo shows how to deploy AMD SEV enabled Confidential Containers on a Kubernetes node that has been configured with CXL memory. Confidential Container is an opensource project in CNCF. The community project supports confidential computing by leveraging trusted execution environments to protect containers and data. The Confidential Container software stack with SEV support is fully upstreamed and works out of the box with CXL.
Astera Labs — CXL™ from Promise to Reality with Real Silicon on Customer Platforms
Astera Labs’ Leo Smart Memory Controller overcomes processor memory bottlenecks and capacity limitations to increase performance and reduce TCO for applications ranging from Artificial Intelligence and Machine Learning to in-memory databases. In this demo, Astera Labs will showcase real CXL silicon running real workloads and performance benchmarks on customer platforms.
Elastics.cloud — Rack-Scale Memory Pooling with CXL
Elastics.cloud demonstrates CXL-enabled rack-scale memory expansion and pooling. Four servers are connected via CXL within a rack, with each server accessing the CXL-attached memory in all other servers.
Intel – CXL™ Type 2 Compliance & Traffic Demo using 4th Gen Intel® Xeon® Scalable Processors and Intel FPGAs
Watch live demonstrations of CXL Type 2 tests: (1) pre-release version of CXL compliance testing (CV App) for Type 2, and (2) a CXL Traffic Generator for Type 2 data transactions (cxl.cache and cxl.mem). Demonstration uses the following ingredients: 4th Gen Intel® Xeon® Scalable Processors in Intel Archer City CRB, Intel® AgilexTM I-Series Development Kit (B0 variant), Intel FPGA CXL IP, FPGA design example and CXL hard/soft IP generated by Intel Quartus 22.3, CXL IP p/n = IP=CXLTYP2.
IntelliProp – Disaggregated and Composable CXL attached Memory Fabric
IntelliProp developed the industry’s first fully disaggregated and composable memory fabric that is scalable to millions of fabric nodes. This demo features a fabric physically located in Longmont, Colorado, while managed and composed live with software running in the CXL Consortium booth.
MemVerge – Software for Memory Visualization, Tiering & Pooling
At SC22, MemVerge is demonstrating Memory Viewer and Memory Machine software for CXL. You will see Memory viewer discovering and visualizing the physical layout of memory on the DDR and CXL busses, while the process monitor “heatmap” shows memory bandwidth usage and utilization by workload. Attendees will also see how Memory Machine software provides a Redis workload with transparent access to a pool of DDR and CXL memory tiered by Memory Machine.
Microchip — CXL™-Based SMC 2000 Smart Memory Controllers
DAX/System-RAM data flows and management.
Rambus — CXL Memory Expansion with Intel Archer City PDK
The Rambus demo will provide a live demo of a functional CXL Type 3 endpoint, leveraging Rambus CXL 2.0 IP. Interoperability, including discovery and CXL.mem read and write transactions, will be shown with an Intel Archer City PDK. The demo will illustrate the following: Linkup, CXL enumeration, CXL .mem read/write tests, and CXLCV compliance test pass (CXL 1.1).
Samsung – AI/ML Application on CXL Memory Expander with Scalable Memory Development Kit (SMDK)
Samsung Electronics Co., Ltd., the world leader in advanced memory technology, announced the industry’s first Compute Express Link (CXL) Memory Expander this year. This demo shows how users can configure and run applications on CXL Memory Expander. It also shows how application can extend memory with CXL Memory Expander. The SMDK (Scalable Memory Development Kit) is an open source software that allows the CXL Memory Expander to work seamlessly with main memory without having to modify existing software code.
Synopsys Inc. — Synopsys CXL™ 2.0 IP Successful Interoperability and Compliance Testing
Synopsys is demonstrating the CXL 2.0 device IP interoperating with the Teledyne LeCroy Z5-16 Exerciser operating as host and running CXL compliance tests.
UnifabriX — CXL™-based Smart Memory Node™
UnifabriX will showcase its Smart Memory Node based on UnifabriX RPU. The demonstration will involve multiple CXL-capable servers connected to two Smart Memory Nodes that are connected through the first ever CXL 3.0 fabric. The CPUs will be able to access local memory, as well as remote memory across. It will also mark the first live demonstration to show enhanced performance related to core utilization, memory capacity, and bandwidth according to a recognized HPC framework.
Xconn Technologies — CXL™ Memory Pooling with a CXL Switch
In order to fully realize the capabilities of CXL, scalable interconnects are required. The addition of CXL switch devices supports sharing and pooling of large memory configurations (> 10TB with a single switch). Xconn Technologies' revolutionary CXL switch ASIC is used to demonstrate memory pooling with the latest server processors and CXL memory devices.
Presentation: Exhibitor Forum (Room D171)
Wednesday, November 16 @ 11:00 am
Title: Introducing CXL 3.0 for increased scale and optimized resource utilization and CXL technology demos
Presenter: Kurt Lender (Intel)
Presentation: Birds of a Feather (Room D167)
Thursday, November 17 @ 12:15 pm
Title: A Look Into the Compute Express Link™ (CXL™) Device Ecosystem
Moderator: Kurtis Bowman (AMD)
Participants: Sandeep Dattaprasad (Astera Labs), Kurt Lender (Intel), Cheolmin Park (Samsung), Jerry Lotto (Synopsys)