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Compute Express Link: The Breakthrough CPU-to-Device Interconnect

CXL Demos at SC'22

CXL Consortium members showcased CXL technology demonstrations on memory solutions, IP, compliance testing, fabric implementations, switches, and software solutions at Supercomputing (SC'22). Learn more about the CXL technology demos below and ask your questions during the live Q&A. 


AMD – AMD SEV Enabled Confidential Containers on CXL Encrypted Memory





Astera Labs — CXL™ from Promise to Reality with Real Silicon on Customer Platforms




 — Rack-Scale Memory Pooling with CXL



Intel – CXL™  Type 2 Compliance & Traffic Demo using 4th Gen Intel® Xeon® Scalable Processors and Intel FPGAs

Intel showed CXL Type 2 tests: (1) pre-release version of CXL compliance testing (CV App) for Type 2, and (2) a CXL Traffic Generator for Type 2 data transactions (cxl.cache and cxl.mem). The demo uses the following ingredients: 4th Gen Intel® Xeon® Scalable Processors in Intel Archer City CRB, Intel® AgilexTM I-Series Development Kit (B0 variant),  Intel FPGA CXL IP, FPGA design example and CXL hard/soft IP generated by Intel Quartus 22.3, CXL IP p/n = IP=CXLTYP2.  

IntelliProp – Disaggregated and Composable CXL attached Memory Fabric

MemVerge – Software for Memory Visualization, Tiering & Pooling

At SC'22, MemVerge demonstrated the Memory Viewer and Memory Machine software for CXL. The demo showcased the Memory viewer discovering and visualizing the physical layout of memory on the DDR and CXL busses, while the process monitor “heatmap” shows memory bandwidth usage and utilization by workload. Attendees gained a better understanding of how the Memory Machine software provides a Redis workload with transparent access to a pool of DDR and CXL memory tiered by Memory Machine.

Microchip — CXL™-Based SMC 2000 Smart Memory Controllers

This year Microchip showcased the DAX/System-RAM data flows and management.

Rambus — CXL Memory Expansion with Intel Archer City PDK

Rambus provided a live demo of a functional CXL Type 3 endpoint, leveraging Rambus CXL 2.0 IP. Interoperability, including discovery and CXL.mem read and write transactions, will be shown with an Intel Archer City PDK. The demo illustrated the following: Linkup, CXL enumeration, CXL .mem read/write tests, and CXLCV compliance test pass (CXL 1.1).

Samsung – Memory Capacity and Bandwidth Expansion with Samsung’s CXL Memory Expander and Scalable Memory Development Kit (SMDK)

Learn more about the Samsung Memory Expander here

Synopsys Inc. – Synopsys CXL™ 2.0 IP Successful Interoperability and Compliance Testing








Teledyne LeCroy 

Teledyne LeCroy provides test equipment for protocol analysis and generation to support development, debug and compliance testing of CXL based devices. Learn more about the Teledyne LeCroy CXL Protocol Analyzers and Exercisers here

UnifabriX — CXL™-based Smart Memory Node™ 


Xconn Technologies — CXL™ Memory Pooling with a CXL Switch

In order to fully realize the capabilities of CXL, scalable interconnects are required. The addition of CXL switch devices supports sharing and pooling of large memory configurations (> 10TB with a single switch). Xconn Technologies' revolutionary CXL switch ASIC is used to demonstrate memory pooling with the latest server processors and CXL memory devices. Learn more here

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