You Asked, We Answered! Answers to Your CXL Consortium™ Webinar Questions
By Glenn Ward, CXL Consortium MWG Co-Chair
I recently moderated our first CXL Consortium webinar, “Introduction to Compute Express Link™.” We had many great questions come in during the Q&A portion, but ran out of time to get to them all. To address them, we’ve provided answers to your questions below.
If you were unable to join the live session, the full webinar recording is available, and you can download the pdf of the presentation here. If you’d like to be notified about our next webinar in Q1, please register on the CXL Consortium BrightTalk channel.
Your CXL Consortium webinar questions answered...
Does CXL provide coherency in virtual address space or in real address space?
CXL technology coherency is in the physical address space (not in the virtual address space). Devices are required to use the Address Translation Service defined in the PCI Express® specification through the CXL.io protocol to request the TLB (Translation Look Aside Buffer) entries and perform the virtual to physical address translation so that requests in the CXL.Cache can be made in the physical address space.
Is there a plan to extend CXL to have inter-device data coherency support?
CXL Links are between the host processor and a device. Thus, multiple devices can access the same cache line by going through their corresponding Links to the host processor(s). For example, multiple devices can cache the same line in their respective caches in the shared state as can the host processor. The host processor has the Home Agent which will orchestrate the cache coherency flows across all the caching agents in the system.
Does CXL support persistent memory?
CXL supports memory extensions for any type of memory, including persistent memory. However, we are considering providing additional enhancements for explicit handshakes on persistence commits in a future revision of the specification.
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