Upcoming Webinar: CXL™ 2.0 Specification – Memory Pooling

By Scott Knowlton

Join us for the upcoming “Compute Express Link™ 2.0 Specification: Memory Pooling” educational webinar airing Tuesday, March 23, 2021, from 9-10 am PT. Last November, the CXL Consortium announced the CXL 2.0 specification which introduces support for switching, memory pooling, and persistent memory – all while preserving industry investments by supporting full backward compatibility with CXL 1.1.

In this webinar, you will:

• Learn how CXL 2.0 supports memory pooling for multiple logical devices (MLD) as well as a single logical device with the help of a CXL switch.

• Understand how the CXL switch enables servers to pool resources such as accelerators and/or memory that can be assigned to different servers depending on the workload.

• Explore the standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric solutions.

• Immediately following the presentation, we will be hosting a live, interactive Q&A discussion to address attendee questions.

Webinar presenters:

• Mahesh Wagh, CXL Consortium Protocol Working Group Co-Chair and Senior Principal Engineer, Intel Corporation

• Rick Sodke, Associate Technical Fellow, Microchip Technology Inc.

Register now!

Learn more about the CXL 2.0 specification:

• Introducing the Compute Express Link™ 2.0 Specification Webinar

• Compute Express Link™ 2.0 White Paper

• Evaluation Copy of the Compute Express Link™ 2.0 Specification

Follow CXL Consortium on Twitter and LinkedIn for updates!