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Join Us: “Compute Express Link™ (CXL™): Memory Challenges and CXL Solutions” Webinar

Updated: Jul 16

August 6, 2020 from 8 AM – 9 AM PT


By Scott Knowlton


We are continuing our educational webinars on CXL and our next one is focused on how CXL can address the memory challenges designers are facing with new emerging applications. I encourage you to register for our upcoming webinar “Compute Express Link™ (CXL™): Memory Challenges and CXL Solutions” to learn more about the benefits of using CXL. CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CXL.io, based on PCIe®), caching (CXL.cache) and memory (CXL.mem) semantics. CXL.mem allows a host processor to access memory attached to a CXL device. CXL.mem transactions are simple memory load and store transactions that run downstream from the host processor which takes care of all the associated coherency flows.


There are three different use cases for CXL referred to as Type 1 Device, Type 2 Device and Type 3 Device.

  • Type 1 Device is for caching devices or accelerators and uses CXL.io and CXL.cache protocols

  • Type 2 Device is for accelerators with memory and uses CXL.io, CXL.cache and CXL.mem

  • Type 3 Device is for memory buffers and uses CXL.io and CXL.mem

In this webinar, you will:

  • Learn about the current trends and challenges of memory

  • Understand how the CXL.mem protocol can deliver power-efficient performance for emerging applications such as artificial intelligence, high performance computing, and deep learning

  • Explore CXL Type 3 Device and use cases for memory bandwidth expansion, memory capacity expansion and storage class memory

Webinar presenters:

  • Chris Petersen, CXL Consortium Director, CXL Consortium Memory Systems Working Group Chair and Hardware Systems Technologist, Facebook

  • Prakash Chauhan, CXL Consortium Director and Systems Architect, Google

Register now!


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Compute Express Link™ and CXL™ Consortium are trademarks of the Compute Express Link Consortium.

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