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CXL™ Consortium Member Spotlight: Astera Labs

Updated: Aug 22


CXL™ Consortium member company Astera Labs recently participated in a Q&A session to discuss the benefits of CXL Consortium membership, its contributions to CXL and ideal targets for CXL technology.


Can you share a brief introduction of Astera Labs?

Astera Labs is a fabless and cloud-based semiconductor company developing purpose-built connectivity solutions to overcome performance bottlenecks throughout the modern data center and realize the vision of Artificial Intelligence (AI) in the cloud. With our relentless focus on exponential innovation and execution, Astera Labs was the first to market with PCIe® 5.0 and Compute Express Link™ (CXL™) 1.1/2.0 Smart Retimers and 100G/Lane Ethernet Smart Cable Modules for rack-to-rack connectivity. The company has continued to push the boundaries of high-performance connectivity in the cloud with the industry’s first CXL based memory pooling and expansion SoC platform specifically developed for large-scale cloud deployment.


Rather than taking an incremental approach to solving bandwidth, capacity, and performance bottlenecks, we are partnering with the world's leading cloud service providers, CPU/GPU/AIP vendors, and system integrators to develop purpose-built, system-aware connectivity solutions for a composable, disaggregated and scalable data center infrastructure. Astera Labs is headquartered in Santa Clara, CA and has offices around the world.


Why did Astera Labs decide to join the CXL™ Consortium?

Astera Labs was amongst the first companies to recognize the need to develop solutions for heterogeneous computing and envisioned the products required to address connectivity bottlenecks throughout the data center. Astera Labs has long-standing relationships with the customers and ecosystem partners required to develop these solutions, and we recognize the value of an open standard to align our partners and customers to a common goal. We joined the CXL Consortium to contribute towards the development of CXL specifications while pioneering the next generation high-speed interconnect technologies.


What expertise does Astera Labs bring to the consortium?

Our silicon technology, development process, and engineering teams are all purpose-built to solve connectivity challenges in complex, data-centric systems. Building on deep market and technical expertise in high-speed interface technology, Astera Labs has introduced three product families addressing data and memory connectivity bottlenecks in data centers and has established itself as a leader in PCIe, Ethernet, and CXL based solutions. By working and developing our silicon products exclusively in the cloud, we understand the pain points and challenges that cloud service providers face, and we build solutions to those challenges from the ground up while emphasizing reduction in Total Cost of Ownership (TCO).


At Astera Labs, we understand that standards compliance and plug-and-play system level interoperability are critical for our customers. For this reason, we have established the industry’s first system-level interop testing platform, Cloud-Scale Interop Lab, to rigorously test our connectivity products like Aries Smart Retimer portfolio for interoperability with all major root complexes and endpoints. Additionally, we plan to expand the Cloud-Scale Interop Lab’s focus and activities to include CXL memory subsystem interoperability testing.


We have established close partnerships with leading processor vendors, memory vendors, server OEMs, and cloud customers to understand their specific requirements, develop SoCs, and contribute to the CXL Consortium to improve the specification and expand adoption of CXL.


What is the biggest advantage of CXL Consortium membership? How does Astera Labs participate?

CXL Consortium membership allows technology and industry leaders such as Astera Labs to contribute towards defining next generation interconnects, architect fabrics for composable infrastructure, collaborate with industry partners to innovate and help solve future connectivity problems of emerging technologies and systems.


Astera Labs has contributed to a variety of CXL 2.0/3.0 working groups and task forces, authored technical material, and conducted training for the CXL community.


What use cases will be ideal targets for CXL technology? Which market segments will benefit from CXL?

Modern day applications such as AI, Machine Learning (ML), and Deep Learning (DL) are generating larger and more complex datasets that require a new generation of computing architectures that can process these datasets in real time. To support these compute-intensive workloads, servers have significantly evolved over the past decade to include processors with higher core counts and multi-socket architectures. However, these servers are still plagued by performance bottlenecks due to lack of memory capacity and bandwidth availability per CPU/GPU core thereby resulting in inefficient and under-utilized usage of processor capabilities. Due to the parallel pin interface of DDR, expansion of local-attached memory to meet these needs is impractical as it presents physical limitations, challenges with signal integrity, and hurdles in optimizing thermal cooling solutions.


The CXL specification, specifically through the CXL.mem protocol, addresses these limitations by enabling robust disaggregated memory pooling and expansion capabilities for processors, workload accelerators, and smart I/O devices to overcome these memory bandwidth and capacity constraints. CXL will address these memory bottlenecks with significant improvements in several emerging compute-intensive use cases, including general-purpose compute, HPC, AI/ML/DL inference training, in-memory databases, multi-tenant use-cases, and other application-specific workloads in enterprise data centers and the cloud.


What does Astera Labs see as CXL’s impact within your industry?

CXL creates a unified, coherent memory interconnect between CPUs, GPUs, Smart NICs, FPGAs, memory devices, and accelerators. This innovative approach to maintaining memory coherency between the CPU memory space and memory on attached devices will revolutionize how HPC and data center server architectures will be built for years to come and will be the foundation to realize the vision of AI in the cloud. Astera Labs is a proud contributor to this exciting technology and is working with key industry leaders to develop the CXL technology, create a robust ecosystem, and accelerate its deployment.


Interested in participating in the CXL Consortium Member Spotlight blog series? Contact press@computeexpresslink.org for details.




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