CXL Demos at SC'23

Compute Express Link™: The Breakthrough CPU-to-Device Interconnect

CXL Consortium member companies showcased live CXL technology demonstrations at the CXL Pavilion (Booth #1301) on memory solutions, fabric implementations, interoperability and compliance testing, and software solutions at Supercomputing (SC'23). Learn more about the CXL technology demos showcased at SC'23 below.

AMD: Enhancing AI with CXL Memory Tiering

Astera Labs: Demonstrating Breakthrough Memory Bandwidth and Performance for HPC and AI with Leo Memory Connectivity Platform
Astera Labs is demonstrating its Leo Smart Memory Controllers, the industry’s highest performant memory controller, enabling CXL-attached memory for memory-intensive AI and HPC workloads. Learn more:

Cadence: Silicon-Proven Subsystem IP for CXL Host and Endpoint from Cadence Live Demo with Viavi Protocol Analyzer

Intel: CXL Memory Modes on Future Generation Intel Xeon CPUs
- Demo 1: Database workload performance enhancement using CXL memory on Intel’s 5th gen Xeon (codename: Emerald Rapids) processor
- Demo 2: System memory TCO reduction using Flat Memory Mode on Intel’s next generation Xeon (codename: Granite Rapids) processor

IntelliProp: Composable and Managed CXL Fabric Demo
IntelliProp’s CXL Extensible Memory Modules enables the composable data center transformation – fundamentally changing the performance, efficiency, and cost of data centers. Learn more by visiting https://intellipropipcores.com/.

Lightelligence: Photowave: Optical CXL Interconnect for Composable Data Center Architectures

The demonstration showcases the benefits of CXL over optics connectivity for large language model (LLM) inference. The AI model is stored in two Micron CXL memory expansion modules which are optically connected by a pair of Photowave PCIe cards to an AMD Genoa CXL 1.1 server and NVIDIA A10 GPU. MemVerge’s memory machine software is utilized to enhance memory performance. A 2.4x improvement in decode throughput is demonstrated using optical CXL memory expansion compared to local SSD memory.

Microchip: HP Memory Capacity & Bandwidth Expansion

The SMC2000, CXL Smart Memory Controller, facilitates HPC applications by increasing the memory capacity available per core and memory bandwidth per core.

Micron: Micron CZ120 Memory Capacity Expansion for AI & HPC Workloads Using CXL
Our Live Demo shows with CXL not only we can increase memory capacity of > 1 TB per CPU, we also showcase performance improvement as we are seeing improved in bandwidth of 18-22%. Learn more by visiting www.micron.com/cxl.

Rambus: CXL Tiered Memory Platform Development Kit for Performant Memory Scaling
This demonstration will preview the high degree of flexibility and configurability offered by the Rambus CXL platform development kit (PDK). Benchmarking software will be running in a production server demonstrating the effective use of memory tiering through the Rambus CXL PDK. Audience members will be encouraged to customize and update the PDK’s behavior using in-box CXL management utilities. The demo will demonstrate how the PDK can apply these updates live without impacting the benchmarking software’s operation or requiring a host reboot. Learn more here.

Samsung: Graph DB Application on CXL Memory Enabled System
By sharing the Nebula DB bench performance measurement using CXL Memory Expander (CMM-D), Samsung shows the potential benefits in various applications (in memory databases, AI training, etc.) of CMM-D. Due to an increase in data explosion & I/O traffic, a new protocol for CPU-accelerator and high capacity & bandwidth memory is needed. Samsung has been researching the better solution by re-architecting with CXL(CMM-D). Through SC23 Samsung will show the possibility of CXL. Learn more here.

Siemens EDA: CXL Performance Optimization & Validation SW Development Kit
Demonstrate targeted CXL Performance and Validation Suite under CPDK (CXL Performance Development Kit) running under Linux on a CXL 2.0/3.0 system. Demonstration targets include both pre-silicon QEMU/KVM/Co-Sim virtual environment and post-silicon Sapphire Rapids server with industry leading CXL memory expansion platforms.

CPDK (CXL Performance Development Kit) supports performance benchmarking and validation framework for fine-grained verification and performance and latency measurements. CPDK supports pre-defined and customizable high memory access stress workloads including select industry distributed, in-memory enterprise software applications such as REDIS. In this demonstration, standard REDIS runs over CPDK library to stress test and performance characterize CXL under real application conditions. CPDK library achieves this goal by controlling memory access patterns to directly target CXL memory and mitigate caching effects.

CXL/PCIe Virtual Platform Solutions

Synopsys / Teledyne LeCroy: CXL 2.0 Interop and Compliance Testing with Teledyne LeCroy Summit Z516 Protocol Exerciser
Teledyne LeCroy and Synopsys are showcasing at SC’23 protocol analysis and compliance testing of CXL based devices through a demo interop using Synopsys CXL 2.0 complete solution and the Teledyne LeCroy Summit Z516 Protocol Exerciser.
- Learn more about the Teledyne LeCroy CXL Protocol Analyzers and Exercisers here.
- Learn more about Synopsys CXL IP complete solution with controller, PHY, IDE Security Modules and Verification IP here.

UniFabrix: MAXimize HPC and AI Speed with: MAX™ memory and Storage Machine
Watch the UnifabriX MAX live demo! On-demand, workload-aware, high-performance provisioning of memory capacity and bandwidth!
Welcome to the era of memory acceleration… Turbocharge your AI with UnifabriX MAX! Come see performance gain for industry-standard benchmarks.

Viavi: CXL 2.0 Exerciser and Analyzer System
VIAVI CXL protocol test solutions provide tools necessary to debug, analyze and perform validation of CXL links on an integrated exerciser and analyzer platform. To learn more visit: VIAVI CXL test solutions.

Xconn Technologies: CXL 2.0 Memory Pooling (Sharing) Using Xconn Switch
XConn Technologies demos a composable memory system (CMS) through using XConn's CXL 2.0 switch and a number of CXL memory expander devices such as devices from Samsung, Micron and SmartModular. With the software from partner companies, XConn demoed a working prototype of memory pooling, and even further memory sharing through software support.

ZeroPoint Technologies: Hardware Accelerated CXL Memory Compression
ZeroPoint Technologies will demonstrate an integrated, Hardware Accelerated Compression Engine, seamlessly adding a new Compressed CXL Memory tier to the system Memory Hierarchy.

Background: Hyperscaler end customers like Meta and Google employ software data compression today in production to tier memory into 3 level hierarchy: DRAM, software Compressed DRAM and SSD. They spend up to 5% of all data center CPU cycles performing software compression/ decompression as a background activity. As hyperscalers evaluate the TCO of introducing CXL as a new tier of pooled/shared memory, Transparent, inline hardware Hccelerated Compression Offload to a CXL Type 3 device operating at memory speeds can increase effective memory capacity by 2-3X and increase effective bandwidth by 50%, and save upto 5% CPU cycles to be redirected to Revenue generating services, making a compelling TCO case to deploy CXL at scale.

Product Link: https://www.zeropoint-tech.com/news/zeropoint-ip-offerings-updated-overview-released